Semiconductor memory devices, such as Dynamic Random Access Memory (DRAM) devices, usually charge bit lines up to a predetermined voltage (e.g., Vcc/2) in order to read or write information from/to a memory cell or to close an activated bank of memory cells. In these devices, before opening a new row of an activated bank, the activated bank should be precharged by way of a precharge function or an auto-precharge command. For instance, the read and write commands of dual data rate synchronomous dynamic random access memory devices (DDR SDRAM) generally automatically precharge the activated bank of memory cells during a burst read cycle or a write cycle by receiving a specific address signal (e.g., a column address A10) in accordance with the timing of a column address strobe (/CAS) signal. If the column address A10 is set to a high level when the read or write command is introduced, an auto-precharge operation begins. A read command assigned to the auto-precharge operation is executed in the same pattern with a normal read command except that the precharge operation starts at a rising edge of the clock cycle of the column address strobe (/CAS) signal prior to the end of the read burst packet. The auto-precharge operation may also be activated by a write-command. The auto-precharge operation may not start until all of the data contained within a burst write sequence is stored in the memory array. The above-described control for initiation of the auto-precharge operation may enhance the asymmetric performance of the device by preventing the burst operation from being disturbed by the precharge operation.
FIG. 1A is a timing diagram showing a conventional read operation of a DDR DRAM device that does not include an auto-precharge capability. To facilitate the explanation of how the device operates, it is assumed that the DDR DRAM operates with a row cycle time tRC of 10 clock cycles (10*tCK), a /RAS-to-CAS delay time tRCD of 3 clock cycles (3*tCK), and a /CAS latency (CL) of 2 clock cycles (2*tCK). In addition, it is assumed that the memory cell array of the DDR DRAM is divided into 4 banks. In FIG. 1A, A0–A3 represent the first through fourth active row commands, R0–R3 represent the first through fourth read commands, and P0–P3 represent the first through fourth precharge commands to the 4 respective banks of the device.
Referring to FIG. 1A, the first active row command A0 is input at clock cycle T0. The read command R0 is then input after tRCD at clock cycle T3. The second active row command A1 is input at clock cycle T2, and then the second read command R1, which corresponds to the second active row command A1, is input after tRCD at clock cycle T5. The third active row command A2 is input at clock cycle T4, and then the corresponding third read command R2 is input after tRCD at clock cycle T7. The fourth active row command A3 is input at clock cycle T6 and, then the corresponding fourth active read command R3 is input after tRCD at clock cycle T9.
As if further shown in FIG. 1A, after the lapse of the two clock cycles (corresponding to CL=2) from the clock cycle at which the first read command R0 is input (i.e., clock cycle T3), a first data bit Q0 is output to a data I/O signal line DQ at clock cycle T5. After two clock cycles (corresponding to CL=2) from the clock cycle T5 at which the second read command R1 is input, a second data bit Q1 is output at clock cycle T7. Similarly, after two clock cycles (corresponding to CL=2) from the clock cycle T7 when the third read command R2 is input, a third data bit Q2 is output at clock cycle T9, and after two clock cycles (corresponding to CL=2) from the clock cycle T9 at which the fourth read command R3 is input, a fourth data bit Q3 is output at clock cycle T11.
After expiration of the row cycle time tRC, the first active row command A0 is again input at clock cycle T10. If the column address of the first active row command A0 at clock cycle T0 is different from the column address of the first active row command A0 at clock cycle T10, the first precharge command P0 should be applied before the first active row command A0 is received at clock cycle T10. In FIG. 1A, the first precharge command P0 is input at clock cycle T8. Similarly, if the column address of the second active row command A1 that is input at clock cycle T2 is different from the column address of the second active row command A1 that is input at clock cycle T14, a second precharge command P1 is input at clock cycle T11 before the second row command A1 is received.
As illustrated above, the conventional read operation of a DDR DRAM that does not include an auto-precharge capability uses active row-read-precharge commands. As illustrated in FIG. 1A, this results in idle periods during clock cycles T13–T14 and T17–T18 during which data is not transferred through the bus lines of the memory system. These idle periods generally degrade the transmission efficiency of the device.
Auto-precharge commands have been employed to address this efficiency problem. In particular, a read command that includes an auto-precharge function or capability (hereinafter, referred to as an auto-precharge read command or “RA”) or a write command that includes an auto-precharge capability (WA) may be used to carry out the precharge operation after the completion of a read or write operation without the need for a separate precharge command. FIG. 1B is a timing diagram showing the timing for a read operation in a conventional DDR DRAM that includes such an auto-precharge capability.
As shown in FIG. 1B, the first active row command A0 is input at clock cycle T0, and then a first auto-precharge read command RA0 is input after tRCD at clock cycle T3. The second active row command A1 is input at clock cycle T2, and then the second auto-precharge read command RA1 is input after tRCD at clock cycle T5. The third active row command A2 is input at clock cycle T4, and then the third auto-precharge read command RA2 is input after tRCD at clock cycle T7. The fourth active row command A3 is input at clock cycle T6, and then the fourth auto-precharge read command RA3 is input after tRCD at clock cycle T9. After two clock cycles (corresponding to CL=2) from clock cycle T3 at which the first auto-precharge read command RA0 is input, the first data bit Q0 is output at clock cycle T5 to the data I/O signal line DQ. Similarly, two clock cycles after the second auto-precharge read command RA1 is input at clock cycle T5, the second data bit Q1 is output at clock cycle T7. Two clock cycles after clock cycle T7 at which the third auto-precharge read command RA2 is input, the third data bit Q2 is output at clock cycle T9. Two clock cycles after clock cycle T9 at which the fourth auto-precharge read command RA3 is input, the fourth data bit Q3 is output at clock cycle T11.
At clock cycle T3, a corresponding bank is precharged by the first auto-precharge read command RA0. This allows the semiconductor memory device to operate without the need for an additional precharge command in advance of the input of the first active row command A0 at clock cycle T10. As is clear from a comparison of FIGS. 1A and 1B, this can improve the efficiency of the data bus. However, inefficiencies still exist when an auto-precharge read or write command is used because the row that was opened is automatically closed after the read or write operation (i.e., all cells sensed by the active row command). Thus, the active row command should be enabled again in order to access the same row after several clock cycles. As the row is typically not available to conduct a page mode operation that accesses a previously sensed row without a further active row command, the latency time in the memory may be lengthened, degrading the performance efficiency of the memory device.
Analysis of typical data processing programs reveals that there is a tendency for strings of consecutive read and write operations to be concentrated in a localized region of the memory device. This tends to occur because many computer programs employ a large number of program loops and subroutines that are performed in sequential steps. As such, the memory cell that is to be accessed during a read or write operation will, in many instances, comprise a previously accessed memory cell or a memory cell locally adjacent to a previously accessed memory cell. The page mode operation applies cache theory to the operation of the DRAM device. A page of a DRAM device is defined as the number of cells simultaneously selected by one active row command. The size of a page thus may be computed as 2row address bits*I/O bits. Thus, for example, in the case of a DRAM device having 10 row address bits and 8 data pins, the page size (or capacity) is 210*8=8192 bits. Therefore, if a specific memory cell within a particular 8192 bit page is accessed, the next memory cell accessed may likely also be another one of the memory cells corresponding to a cell within the 8192 bits. When the page mode is used for a read or write operation, a page opened by an active row command typically maintains its open state without precharging. If the next address for a read or write operation is an address within the already opened page, the read or write operation can be performed without an additional active row command. In this manner, the use of page mode operations may contribute to improved operational performance of the memory device. However, when a conventional DRAM employs the auto-precharge function with the page mode as shown in FIG. 1B, page mode operation may not be available because a page that is opened may be closed after the completion of the read or write operation.